High speed digital (HSD) serial-deserializer (SerDes) system channel simulation is critical for SerDes system design and validation. The simulation must run fast while achieving adequate accuracy. Today’s SerDes system vendors require HSD IBIS-AMI (Input/Output Buffer Information – Algorithmic Modeling Interface) models long before silicon is available. To meet the demand, HSD silicon vendors desire an […]
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Using IBIS Package Data in ADS
For high speed digital (HSD) integrated circuits (ICs) used in Serializer/Deserializer (SerDes) systems, signal integrity (SI) engineers often convert such circuits into Input/Output Buffer Information specification (IBIS) models to achieve fast simulations for evaluation and performance prediction. One common modeling task is to model the interconnects between board level components. These interconnects are often modeled […]
Using IBIS Electronic Board Data in ADS
For high speed digital (HSD) integrated circuits (ICs) used in Serializer/Deserializer (SerDes) systems, signal integrity (SI) engineers often convert such circuits into Input/Output Buffer Information specification (IBIS) models to achieve fast simulations for evaluation and performance prediction. One common modeling task is to model the interconnects between board level components. These interconnects are often modeled […]
Statistical Model Development for High Speed SerDes
IBIS Algorithmic Modeling Interface (IBIS-AMI) defines two approaches to SerDes modeling and simulation flow: time domain or bit-by-bit simulation for nonlinear and/or time variant (NLTV) model and statistical simulation for linear and time invariant (LTI) model. Statistical simulation has advantages of faster simulation speed and arbitrary low BER floor under linear model assumption. However, the […]
Modeling a SerDes System with a Redriver Between Two Channels
High speed digital (HSD) integrated circuits (ICs) are used in Serializer/Deserializer (SerDes) systems defined at a high data rate with a lossy channel between the transmitter circuit and the receiver circuit. In such systems, the received data stream is severely distorted and requires reconstruction (equalization) before use. For system design, there is often the need […]
Modeling a SerDes System with a Retimer Between Two Channels
High speed digital (HSD) integrated circuits (ICs) are used in Serializer/Deserializer (SerDes) systems defined at a high data rate with a lossy channel between the transmitter circuit and the receiver circuit. In such systems, the received data stream is severely distorted and requires reconstruction (equalization) before use. For system design, there is often the need […]
Creating an Adaptive CTLE AMI Model
High speed digital (HSD) integrated circuits (ICs) are used in Serializer/Deserializer (SerDes) systems defined at a high data rate with a lossy channel between the transmitter circuit and the receiver circuit. In such systems, the received data stream is severely distorted and requires reconstruction (equalization) before use. For system design, an adaptive Rx continuous time […]
Using SPICE Frequency Domain Data in CTLE AMI Models
High speed digital (HSD) integrated circuits (ICs) are used in Serializer/Deserializer (SerDes) systems defined at a high data rate with a lossy channel between the transmitter circuit and the receiver circuit. In such systems, the received data stream is severely distorted and requires reconstruction (equalization) before use. One common modeling objective is to use SPICE […]
SerDes System CTLE Basics
High speed digital (HSD) integrated circuits (ICs) are used in Serializer/Deserializer (SerDes) systems defined at a high data rate with a lossy channel between the transmitter circuit and the receiver circuit. In such systems, the received data is severely distorted and needs to be reconstructed (equalized) before use. One common equalizer approach used in transmit […]