For high speed digital (HSD) integrated circuits (ICs) used in Serializer/Deserializer (SerDes) systems, signal integrity (SI) engineers often convert such circuits into Input/Output Buffer Information specification (IBIS) models to achieve fast simulations for evaluation and performance prediction. One common modeling task is to model the interconnects between board level components. These interconnects are often modeled […]
Archive | June, 2013
Using IBIS Electronic Board Data in ADS
For high speed digital (HSD) integrated circuits (ICs) used in Serializer/Deserializer (SerDes) systems, signal integrity (SI) engineers often convert such circuits into Input/Output Buffer Information specification (IBIS) models to achieve fast simulations for evaluation and performance prediction. One common modeling task is to model the interconnects between board level components. These interconnects are often modeled […]
Statistical Model Development for High Speed SerDes
IBIS Algorithmic Modeling Interface (IBIS-AMI) defines two approaches to SerDes modeling and simulation flow: time domain or bit-by-bit simulation for nonlinear and/or time variant (NLTV) model and statistical simulation for linear and time invariant (LTI) model. Statistical simulation has advantages of faster simulation speed and arbitrary low BER floor under linear model assumption. However, the […]