High speed digital (HSD) integrated circuits (ICs) are used in Serializer/Deserializer (SerDes) systems defined at a high data rate with a lossy channel between the transmitter circuit and the receiver circuit. In such systems, the received data stream is severely distorted and requires reconstruction (equalization) before use. One common modeling objective is to use SPICE simulation data from analog transistor level circuits to model a continuous time linear equalizer (CTLE) based on the IBIS Algorithmic Model Interface (AMI). Such a CTLE model often has many defined states for use in the circuit. There may be 10s, 100s or 1000s of states, each controlled by a digital word in the CTLE circuit.
This modeling work is typically done by signal integrity (SI) engineers to convert circuits into Input/Output Buffer Information specification (IBIS) models using the IBIS AMI (Algorithmic Modeling Interface) standard to achieve fast simulations for evaluation and performance prediction.
See the full article: Using_SPICE_Frequency_Domain_Data_in_CTLE_AMI_Models
Download the application zip file: NState_CTLE
