High speed digital (HSD) integrated circuits (ICs) are used in Serializer/Deserializer (SerDes) systems defined at a high data rate with a lossy channel between the transmitter circuit and the receiver circuit. In such systems, the received data is severely distorted and needs to be reconstructed (equalized) before use. One common equalizer approach used in transmit and receive circuits is a continuous time linear equalizer (CTLE). This article discusses CTLE characteristics in the time and frequency domain. The algorithmic point of view is presented and not the actual circuit implementation point of view.
This modeling work is typically done by signal integrity (SI) engineers to convert circuits into Input/Output Buffer Information specification (IBIS) models using the IBIS AMI (Algorithmic Modeling Interface) standard to achieve fast simulations for evaluation and performance prediction.
See article for details: SerDes System CTLE Basics
